1. Field of the Invention
The present invention relates to semiconductor voltage generator circuits, and particularly to capacitive voltage multiplier circuits.
2. Description of the Related Art
Many integrated circuits, particularly those using a single power supply voltage, incorporate on-chip circuitry to generate a “boosted” voltage having a magnitude greater than the power supply voltage. Frequently this boosted voltage is used as a veritable power supply voltage for portions of the circuitry contained on the integrated circuit. For example, certain types of semiconductor memories, such as “flash” EEPROM memories, write a memory cell by accelerating electrons across a tunneling dielectric and storing the charge on a floating gate above a field effect transistor. On contemporary devices, this acceleration of charge across the tunneling dielectric frequently requires a “write voltage” on the order of 8 volts, yet the remainder of the operations of the memory circuitry typically requires a voltage on the order of only 3 volts, including reading the memory cells. Unlike many older devices which require two different power supply voltages be supplied to operate the device (e.g., +5 and +12 volts), many contemporary devices require only a single power supply voltage (usually called VDD) equal to 2.5–3.3 volts (relative to “ground” or VSS). This VDD power supply voltage is typically utilized to power most of the device, including the normal read operation circuits. The write voltage (frequently, although not always, called VPP for legacy reasons) is generated by an on-chip voltage generator having a typical value of +8 volts (again relative to VSS) rather than requiring a separate power supply voltage be supplied by a user of the device.
In many integrated circuits, such on-chip voltage generators are implemented as capacitive voltage multiplier circuits, largely because of the historical ease of implementing suitably large capacitors on a monolithic integrated circuit, especially compared to implementing good quality inductors. These capacitive voltage multiplier circuits are usually called “charge pumps” by those in the art. Not to be confused with capacitive voltage multiplier circuits, there is another class of circuits also frequently called charge pumps. These are frequently used to integrate small current pulses generated each cycle by a phase detector circuit, and to consequently generate an analog voltage on a capacitor node which represents the phase error between two phase detector input signals. During each cycle, a typical phase detector “pumps” a first current pulse into the capacitor node and “pumps” a second current pulse from the capacitor node. If the phase error is zero, these two current pulses are equal, and the voltage on the capacitor node is unchanged. But if the phase of one input signal lags the other, one of the current pulses is greater in magnitude, or longer in duration, or both, so that the net charge into the capacitor node is non-zero, and a voltage change results. Such “phase detector integrator” charge pumps are quite different in both function and structure, and are consequently not considered to be related to capacitive voltage multiplier circuits. Consequently, as used herein, a “charge pump” refers to a capacitive voltage multiplier circuit and not to such phase detector integrator circuits, unless the context so requires.
In the nonvolatile memory example described above, the write voltage generated by the charge pump is typically higher than the VDD power supply voltage provided to the device. In other integrated circuits, a charge pump may be used to generate a voltage below the reference voltage VSS (i.e., “below ground”). For example, a negative bias voltage is generated in many memory devices such as dynamic random access memories (DRAMs), static random access memories (SRAMs), and other circuits, to bias a substrate and/or a CMOS well within the substrate.
Referring now to FIG. 1, a schematic diagram of a traditional (and very well known) charge pump circuit for generating a boosted voltage above VDD is shown, which circuit is taught by John F. Dickson in “On-Chip High-Voltage Generation in NMOS Integrated Circuits Using an Improved Voltage Multiplier Technique,” IEEE Journal of Solid State Circuits, Vol. SC-11, No. 3, June 1976, pp. 374–378. The charge pump 100 includes a plurality of serially-connected charge pump stages, one of which is labeled 102. Each charge pump stage includes a charge transfer device, such as diode 104, and a pump capacitor, such as capacitor 106, and has an input node, such as node 108, and an output node, such as node 110. A complementary pair of clock signals CLK and /CLK (labeled in the figure as CLK “bar” with the traditional inverting “bar” over the name) are provided to drive the various pump stage capacitors. Odd-numbered (or alternately even-numbered) pump stages are driven by the CLK signal, while even-numbered (alternately odd-numbered) pump stages are driven by the /CLK signal. The input node of the first serially-connected charge pump stage, here labeled as node 111, is usually connected to the VDD power supply (at least for generating a positive boosted voltage). A final isolation diode 114 may be considered as part of the last serially-connected charge pump stage, and the output voltage of the charge pump 100 taken from node 116 rather than from node 112 (which would otherwise be considered the output node of the last serially-connected charge pump stage).
The complementary clock signals are usually driven with full VDD-level swings (i.e., transitioning between a low level of VSS and a high level of VDD). Consequently, each charge pump stage boosts the voltage conveyed to its input node by an amount equal to VDD less a diode drop (assuming relatively negligible DC current and ignoring second order effects). Including the effect of the last isolating diode 114, the maximum theoretical output voltage achievable from such a charge pump 100 is equal to VDD(N)−VDIODE(N+1), where N is the number of charge pump stages and VDIODE is the forward diode drop. In practice, the diodes are frequently implemented as diode-connected FETs (field effect transistors), each with its gate terminal and drain terminal connected together to form one terminal of the diode, and its source terminal forming the other terminal of the diode. Also, the capacitors are frequently implemented as large area FETs, each with its source terminal and drain terminal connected together to form one terminal of the capacitor, and its gate terminal forming the other terminal of the capacitor. Furthermore, the output voltage is usually somewhat less than this theoretical value, due to stray capacitances, incomplete charge transfer, DC current flow provided into the output node, and other effects, which have been well studied in the literature.
At lower power supply voltages, the diode drop lost by each charge pump stage significantly affects the final output voltage achievable by such a charge pump circuit. Consequently, other charge pump circuits replace the diode charge transfer device with a charge transfer switch device (or charge transfer switch, CTS) in each charge pump stage. Referring now to FIG. 2, such a charge pump stage 120 includes a charge transfer switch 126 connecting an input 122 to an output 124, a pump capacitor 128 connected to the output 124, and a control circuit 130 for generating a control node 132 for the charge transfer switch 126. A pulse input 134 is driven by a clock signal, such as one of a complementary pair of clock signals CLK and /CLK, depending upon the relative placement of the charge pump stage within the charge pump circuit.
It is desirable to control the charge transfer switch 126 to reduce the forward drop across the charge transfer switch 126 when turned on to transfer charge from input to output, and to carefully control the time that the charge transfer switch 126 is turned on to prevent back transfer of charge from output to input. A variety of techniques are found in the art for controlling a charge transfer switch device in attempt to simultaneously achieve these two competing goals. Nevertheless, additional improvements in charge pump circuits are desired.
Moreover, such voltage generator circuits also may consume a significant amount of power relative to the remainder of the circuit, and thus increase the current that must be supplied by the user (e.g., by the VDD power supply). Any increase in power dissipation may also increase the temperature of the die during operation. In a battery-powered environment, any increase in power consumed by a device may have significant implications for battery life, and any additional heat generated may also be difficult to dissipate. Consequently, continued improvements in charge pump circuits are desired.